Arm® Architecture Archives - MicroSys https://microsys.de/product-categories/soms-arm-architecture/ Creating Embedded Systems Mon, 26 Jan 2026 14:21:04 +0000 en-US hourly 1 https://wordpress.org/?v=6.9.1 https://microsys.de/wp-content/uploads/2025/01/cropped-MicroSys_Favicon-32x32.png Arm® Architecture Archives - MicroSys https://microsys.de/product-categories/soms-arm-architecture/ 32 32 miriac® MPX-i.MX95 https://microsys.de/products/miriac-mpx-i-mx95/ Thu, 27 Feb 2025 12:00:22 +0000 https://zm7h237e.web141.alfahosting-server.de/?post_type=products&p=5448 Powerful graphics and AI with energy efficiency and security

 

  • 6 Arm® Cortex®-A55 cores at up to 2,0 GHz, 1 Arm® Cortex®-M7 up to 800MHz
  • 1 Arm® Cortex®-M33 up to 333MHz Arm v8-M supporting Trustzone-M
  • 1 Arm® Mali™ 3D GPU 310

The post miriac® MPX-i.MX95 appeared first on MicroSys.

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CPU
Architecture Arm® Cortex®-A55
Processor NXP® i.MX95
CPU: 6 Arm® Cortex®-A55 cores at up to 2,0 GHz
1 Arm® Cortex®-M7 @ 800MHz
1 Arm® Cortex®-M33 @ 333MHz
DRAM 16 GByte LPDDR5 (x32) up to 6.4GT/s (w/ Inline ECC)
Memory
SD Card 2x (up to) interface on connector (boot source)
Octal-Flash 1x Interface on connector (boot source)
eMMC 1x up to 64GB (Onboard boot source)
EEPROM Yes
Graphic
Graphic 3D GPU, OpenGL® ES 3.2, Vulkan® 1.2, OpenCL™ 3.0, 2D GPU
Ethernet
10GbE 1x XFI/USXGMII
1GbE 2x RGMII
High Speed IO
USB 3.0 1x
USB 2.0 1x
PCIe 2x 1-lane
IO
ADC 1x 8ch / 12bit
I3C 1x (up to)
CAN 4x (up to)
SPI 7x (up to)
FlexSPI 1x
UART 5x (up to)
I2C 7x (up to)
Camera
MIPI-CSI 2x á 4-lane (up to)
Audio
PDM 1x (up to)
SAI 3x (up to)
Display
LVDS 2x á 4-lane (up to)
MIPI-DSI 1x 4-lane (up to)
Security / Safety
Tamper 2x
Additionals
Additional Dev Kit available for immediate start, includes power supply, cables. Linux on SD card
Operating Condition
Operational Temperature -40/+85°C
Temperature sensor Yes
Supply Voltage 5V
RTC RV-3028-C7
Mechanical
Dimensions 82x35mm
Connector Type MXM3.0

Our standard product versions offer what we consider to be the optimum configuration in terms of performance, price, usage and TDP. The product features lists specify the maximum range of functions per interface. However, not all interfaces or functions are always available in parallel. Flexible SERDES multiplexing is one of the reasons for this. In addition, we provide multiple memory expansion options and are also happy to accommodate specific customer wishes. So do not hesitate to contact us directly to discuss your desired configuration.

The post miriac® MPX-i.MX95 appeared first on MicroSys.

]]> miriac® MPX-S32Z2 https://microsys.de/products/miriac-mpx-s32z2/ Wed, 26 Feb 2025 15:22:37 +0000 https://zm7h237e.web141.alfahosting-server.de/?post_type=products&p=5415 Coming soon

 

  • 8 Arm® Cortex®-R52 cores at up to 1 GHz with flexible split/lock configurations: Each Arm Cortex-R52 core includes Arm Neon™ SIMD technology Lockstep Arm® Cortex®-M33 System Manager core
  • DSP/ML processor (25 GFLOPS)
  • 2 GB 16-bit soldered LPDDR4 RAM at 1600 MT/s

The post miriac® MPX-S32Z2 appeared first on MicroSys.

]]>
CPU
Architecture Arm® Cortex®-R52
Processor NXP® S32Z2 CPU:
  • 8 Arm® Cortex®-R52 cores at up to 1 GHz with flexible split/lock configurations
  • Each Arm Cortex-R52 core includes Arm Neon™
  • SIMD technology Lockstep Arm® Cortex®-M33 SystemManager core
  • DSP/ML processor (25 GFLOPS)
    •
    DRAM 2 GB 16-bit soldered LPDDR4 RAM at 1600 MT/s
    Memory
    Flash 512 MB QSPI Flash
    Flash Card Interface for external SD-card (only Interface NOT on board)
    Boot Flash Boot select: QSPI / eMMC / SDHC (only Interface NOT on board)
    eMMC Interface for external and eMMC (only Interface NOT on board)
    Ethernet
    RGMII 2x 1GbE
    IO
    I3C 3x (with I2C support)
    CAN 16x
    CAN XL 2x
    Zipwire 2x
    SENT 7x
    SPI 5x
    FlexRay 2x
    LIN 4x
    Analog Inputs (ADCs) 8x
    JTAG Debug Interface Yes
    Aurora Interface Yes
    Security / Safety
    Security Hardware Security Engine (HSE) for secure boot and accelerated security services
    Safety μ controller to monitor voltages
    Operating Condition
    Power Supply Voltage Single DC power input (+9 V to +30 V)
    Mechanical
    Dimensions 82 mm x 50 mm
    Connector Type MXM3.0

    Our standard product versions offer what we consider to be the optimum configuration in terms of performance, price, usage and TDP. The product features lists specify the maximum range of functions per interface. However, not all interfaces or functions are always available in parallel. Flexible SERDES multiplexing is one of the reasons for this. In addition, we provide multiple memory expansion options and are also happy to accommodate specific customer wishes. So do not hesitate to contact us directly to discuss your desired configuration.

    The post miriac® MPX-S32Z2 appeared first on MicroSys.

    ]]>         miriac® MPX-S32G399A https://microsys.de/products/miriac-mpx-s32g399a/ Tue, 25 Feb 2025 14:50:17 +0000 https://zm7h237e.web141.alfahosting-server.de/?post_type=products&p=5351 Compared to our NXP® S32G2 processor based 1st Gen modules, our NXP® S32G399A processor based MPX-S32G399A System-on-Modules offer up to 2.5x times more applications processing performance, extended memory and higher networking bandwidth and address performance-demanding secure, connected mobility and controller application.

     

    • 8 Arm® Cortex®-A53 cores and 4 Arm® Cortex®-M7 cores including lockstep support
    • Comprehensive connectivity including 18x CAN FD + dedicated protocol engine, furthermore FlexRay, LIN, SPI, Ethernet with TSN, PCI Express®, USB and I²C
    • Hardware Security Engine for secure boot and accelerated security services

    The post miriac® MPX-S32G399A appeared first on MicroSys.

    ]]>
    MPX-S32G-Blockdiagram_01
    S32G3_Blockdiagram_nxp

    Our standard product versions offer what we consider to be the optimum configuration in terms of performance, price, usage and TDP. The product features lists specify the maximum range of functions per interface. However, not all interfaces or functions are always available in parallel. Flexible SERDES multiplexing is one of the reasons for this. In addition, we provide multiple memory expansion options and are also happy to accommodate specific customer wishes. So do not hesitate to contact us directly to discuss your desired configuration.

    CPU
    Architecture Arm® Cortex®-A53
    Processor NXP® S32G399A CPU: 8 Arm® Cortex®-A53 64-bit cores, 4 Arm® Cortex®-M7 dual-core lockstep pairs
    DRAM 4 GB 32-bit soldered LPDDR4 RAM at 3200 MT/s
    Memory
    Flash 64 MB QSPI Flash
    Flash Card Interface for external SD-card multiplexed with eMMC
    Boot Flash Boot select: XSPI, eMMC or external SD card
    eMMC Up to 32 GB
    Ethernet
    2.5 Gbps 1x (up to)
    1 Gbps 4x (up to)
    High Speed IO
    SerDes lanes 4x
    ULPI-USB 1x
    PCIe Yes
    IO
    FlexSPI 4x
    UART 2x
    CAN FD 18x
    FlexRay 2x
    LIN 4x
    I2C 4x
    Analog Inputs (ADCs) 12x
    GPIOs Yes
    JTAG Debug Interface Yes
    Aurora Interface Yes
    Security / Safety
    Security Hardware Security Engine (HSE) for secure boot and accelerated security services
    Safety
  • Advanced hardware and software for safety applications
  • Optional: AEC-Q100 Grade 3 (or I): -40°C to 85°C
    •
    Operating Condition
    Power Supply Voltage Single DC power input (+9 V to +36 V)
    Optional Power Supply Voltage Single DC power input (+6 V to +36 V)
    Power Management Yes
    RTC RV-3028-C7
    Extended Temperature -40 °C to +85 °C
    Mechanical
    Dimensions 82 mm x 50 mm
    Connector Type MXM3.0
    Software / Additional
    Software Support
  • Linux
  • VxWorks (on request)
  • Others (on request)
    •
    Additional
  • All I/O pins available on 314-pin edge connector
  • Low Latency Communication Engine (LLCE) for vehicle networks acceleration
  • Packet Forwarding Engine (PFE) for Ethernet networks acceleration
  • Dev Kit available for immediate start, includes power supply, cables. Linux on SD card
    •
    Name Code Description Status
    miriac® MPX-S32G399A 861703 8 Arm® Cortex®-A53, 1.3 GHz, 4 GB LPDDR4 w ECC, 64 MB NOR Flash, 16 GB eMMC, -40 °C to +85 °C, w SEC active
    Development Kit basic for miriac® MPX-S32G399A 8629
  • miriac® MPX-S32G399A
  • CRX-S32G
  • incl. BSP and accessories
    •      		active
    Block Diagrams
    BSP
    Manual

    Q: Only eth0 (the top RJ45 on ST22) shows up as an interface on the S32G. How can I enable the other ethernet interfaces on the S32G?

    A: If only eth0 shows up, have you checked that the PFE firmware is loaded ok in U-Boot? If yes, you will also have pfe0, pfe1, pfe2

    Q: None of the SJA1110A ethernet ports link up.  I’m guessing this is because I need to load an image on the SJA1110A.Is ST10 the JTAG header to use?  What is J45 on the same header?

    A: Yes, ST10 is the header to use. The other device in the JTAG chain, J45, is the Marvell 10GigE PHY (88X3310P) – which we have discarded on Rev.2 Carriers.

    Q: Will the S32G detect the SJA1110A and forward traffic once an image is loaded or will I need another S32G image? 

    A: The SJA110 will forward traffic with the binary image loaded. But traffic coming from the S32G processor will need to be programmed to the SJA1110

    Q: Is there a QSPI attached to the SJA1110, and is there a way for me to flash the QSPI?

    A: Yes, there is a QSPI Flash attached to the SJA1110 which can be programmed using a Lauterbach debugger

    Q: How do we select the boot mode for the SJA1110A?

    A: When SW3 are both OFF, then you can program the Flash from debugger. When both switches are ON, the SJA1110 will boot from Flash

    Q: In our environment, we need solutions that are available over a very long period of time (up to 15 years). How long are your modules available?

    A: Using NXP CPUs on our SoMs we are able to provide an availability of 15 years from the time of the launch of the CPU. With LTB and long-time stocking we are even able to extend this period.

    The post miriac® MPX-S32G399A appeared first on MicroSys.

    ]]>         miriac® MPX-S32G274A https://microsys.de/products/miriac-mpx-s32g274a/ Mon, 24 Feb 2025 13:42:00 +0000 https://zm7h237e.web141.alfahosting-server.de/?post_type=products&p=5302 The world’s first System-on-Modules based on NXP® S32G vehicle network processors are equipped with the NXP® S32G2 processor. They offer more than 10 times the real-time performance and networking throughput of NXP’s previous vehicle network devices and address the next generation of fail-safe and cyber-secure connected mobility and controller applications.

     

    • 4 Arm® Cortex®-A53 cores and 3 Arm® Cortex®-M7 cores including lockstep support
    • Comprehensive connectivity including 18x CAN FD + dedicated protocol engine, furthermore FlexRay, LIN, SPI, Ethernet with TSN, PCI Express®, USB and I²C
    • Hardware Security Engine for secure boot and accelerated security services

    The post miriac® MPX-S32G274A appeared first on MicroSys.

    ]]>
    MPX-S32G-Blockdiagram_R2
    Blockdiagram_S32G2_2
    CPU
    Architecture Arm® Cortex®-A53
    Processor NXP® S32G274A CPU: 4 Arm® Cortex®-A53 64-bit cores at 1Ghz, 3 Arm® Cortex® M7 dual-cores at 400Mhz
    DRAM 4 GB 32-bit soldered LPDDR4 RAM at 3200MT/s
    Memory
    Flash 64 MB QSPI Flash
    Flash Card Interface for external SD card multiplexed with eMMC
    Boot Flash Boot select: XSPI, eMMC or external SD card
    eMMC up to 32 GB
    Ethernet
    2.5 Gbps 1x (upt to)
    1 Gbps 4x (upt to)
    High Speed IO
    SerDes lanes 4x
    ULPI-USB 1x
    PCIe Yes
    IO
    FlexSPI 4x
    UART 2x
    CAN FD 18x
    FlexRay 2x
    LIN 4x
    I2C 4x
    Analog Inputs (ADCs) 12x
    GPIOs Yes
    JTAG Debug Interface Yes
    Aurora Interface Yes
    Security / Safety
    Security Hardware Security Engine (HSE) for secure boot and accelerated security services
    Safety
  • Advanced hardware and software for safety applications
  • Optional: AEC-Q100 Grade 3 (or I): -40°C to 85°C
    •
    Operating Condition
    Power Supply Voltage Single DC power input (+9 V to +36 V)
    Optional Power Supply Voltage Single DC power input (+6 V to +36 V)
    Typical Power Consumption 3,5 W
    RTC RV-3028-C7
    Temperature 0 °C to 70 °C
    Optional Extended Temperature -40 °C to +85 °C
    Mechanical
    Dimensions 82 mm x 50 mm
    Connector Type MXM3.0
    Software / Additional
    Software Support
  • Linux
  • VxWorks (on request)
  • Others (on request)
    •
    Additional
  • All I/O pins available on 314-pin edge connector
  • Low Latency Communication Engine (LLCE) for vehicle networks acceleration
  • Packet Forwarding Engine (PFE) for Ethernet networks acceleration
  • Dev Kit available for immediate start, includes power supply, cables. Linux on SD card
    •

    Our standard product versions offer what we consider to be the optimum configuration in terms of performance, price, usage and TDP. The product features lists specify the maximum range of functions per interface. However, not all interfaces or functions are always available in parallel. Flexible SERDES multiplexing is one of the reasons for this. In addition, we provide multiple memory expansion options and are also happy to accommodate specific customer wishes. So do not hesitate to contact us directly to discuss your desired configuration.

    Name Code Description Status
    miriac® MPX-S32G274A 858102 4 Arm® Cortex®-A53, 1.0 GHz, 4 GB DDR4L w ECC, 64 MB NOR Flash, 16 GB eMMC, 0 °C to 70 °C, w SEC active
    miriac® MPX-S32G274A 858103 4 Arm® Cortex®-A53, 1.0 GHz, 4 GB DDR4L w ECC, 64 MB NOR Flash, 32 GB eMMC, -40 °C to 85 °C, w SEC active
    Development Kit basic for miriac® MPX-S32G274A 8590
  • miriac® MPX-S32G274A
  • CRX-S32G
  • incl. BSP and accessories
    •      		active
    Block Diagrams
    BSP
    Manual

    Q: Only eth0 (the top RJ45 on ST22) shows up as an interface on the S32G. How can I enable the other ethernet interfaces on the S32G?

    A: If only eth0 shows up, have you checked that the PFE firmware is loaded ok in U-Boot? If yes, you will also have pfe0, pfe1, pfe2

    Q: None of the SJA1110A ethernet ports link up.  I’m guessing this is because I need to load an image on the SJA1110A.Is ST10 the JTAG header to use?  What is J45 on the same header?

    A: Yes, ST10 is the header to use. The other device in the JTAG chain, J45, is the Marvell 10GigE PHY (88X3310P) – which we have discarded on Rev.2 Carriers.

    Q: Will the S32G detect the SJA1110A and forward traffic once an image is loaded or will I need another S32G image? 

    A: The SJA110 will forward traffic with the binary image loaded. But traffic coming from the S32G processor will need to be programmed to the SJA1110

    Q: Is there a QSPI attached to the SJA1110, and is there a way for me to flash the QSPI?

    A: Yes, there is a QSPI Flash attached to the SJA1110 which can be programmed using a Lauterbach debugger

    Q: How do we select the boot mode for the SJA1110A?

    A: When SW3 are both OFF, then you can program the Flash from debugger. When both switches are ON, the SJA1110 will boot from Flash

    Q: In our environment, we need solutions that are available over a very long period of time (up to 15 years). How long are your modules available?

    A: Using NXP CPUs on our SoMs we are able to provide an availability of 15 years from the time of the launch of the CPU. With LTB and long-time stocking we are even able to extend this period.

    The post miriac® MPX-S32G274A appeared first on MicroSys.

    ]]>         miriac® MPX-S32V234 https://microsys.de/products/miriac-mpx-s32v234/ Sun, 23 Feb 2025 15:05:08 +0000 https://zm7h237e.web141.alfahosting-server.de/?post_type=products&p=5384 The MPX-S32V234 is based on a vision processor with quad 64-bit Arm® Cortex®-A53 cores. It offers an image signal processor (ISP), a powerful 3D graphic processor unit (GPU), dual APEX-2 vision accelerators, automotive-grade reliability, functional safety & security capabilities.

     

    • Up to dual 1 GB 32-bit ECC DDR3L RAM
    • Image Cognition: 2x APEX2-CL Dual 32-bit array with 2x32 compute units
    • Serial MIPI-CSI: 2x4 lanes, up to 1.5 Gbps
    • Video encoder/decoder: H.264, 8/10/12-bit, JPEG, 8/12-bit, up to 4 streams

    The post miriac® MPX-S32V234 appeared first on MicroSys.

    ]]>
    MPX-S32V234_Block_Diagram_190905
    NXP_CPU_S32V234_BD_v1
    CPU
    Architecture Arm® Cortex®-A53
    Processor NXP® S32V234 CPU:
  • Quad Arm® Cortex®-A53 cores at up to 1.3 GHz core frequency
  • 1x Cortex® M4 Core for real time processing
    •
    DRAM Up to dual 1 GB 32-bit ECC DDR3L RAM
    Memory
    Flash Card USHDC: 2x 8-bit
    Boot Flash eMMC or external SD card
    Graphic
    Graphics Controller Yes
    LCD Interface 24-bit
    HDMI Interface Yes
    Camera Input Yes
    Ethernet
    1GbE 1x
    High Speed IO
    SerDes lanes 8
    PCIe PCEe Gen2 x1 (RC/EP)
    IO
    UART 2x
    CAN FD 2x
    I2C 3x
    GPIOs Yes
    JTAG Debug Interface Yes
    Security / Safety
    Security Security & Encryption: CSE-FL & AES-128
    Safety FCCU and FCCU output supervision unit
    Operating Condition
    Power Supply Voltage Single +12 V DC power input (+/-25%)
    Typical Power Consumption 4,8 W
    Power Management Yes
    RTC PCF85263
    Temperature 0 °C to 70 °C
    Optional Extended Temperature -40 °C to +85 °C
    Mechanical
    Dimensions 62 mm x 82 mm
    Connector Type MXM3.0
    Software / Additional
    Additional
  • Image Cognition: 2x APEX2-CL Dual 32-bit array with 2x 32 compute units
  • Video encoder/decoder: H.264, 8/10/12-bit / H.264, 8/10/12-bit, JPEG, 8/12-bit, up to 4 streams
  • RCON/serial Boot switch
  • GPU Power disconnect option
  • Dev Kit available for immediate start, includes power supply, cables. Linux on SD card.
    •

    Our standard product versions offer what we consider to be the optimum configuration in terms of performance, price, usage and TDP. The product features lists specify the maximum range of functions per interface. However, not all interfaces or functions are always available in parallel. Flexible SERDES multiplexing is one of the reasons for this. In addition, we provide multiple memory expansion options and are also happy to accommodate specific customer wishes. So do not hesitate to contact us directly to discuss your desired configuration.

    Name Code Description Status
    miriac® MPX-S32V234 854901 4 Arm Cortex® A53, 1.0 GHz, 1 GB DDR3L w ECC, 0° to 70° C, w/o SEC NRND
    Development Kit basic for miriac® MPX-S32V234 8557xx
  • miriac® MPX-S32V234
  • CRX-S32V
  • incl. accessories
    •      		NRND
    Block Diagrams
    Manual

    Q: In our environment, we need solutions that are available over a very long period of time (up to 15 years). How long are your modules available?

    A: Using NXP CPUs on our SoMs we are able to provide an availability of 15 years from the time of the launch of the CPU. With LTB and long-time stocking we are even able to extend this period.

    The post miriac® MPX-S32V234 appeared first on MicroSys.

    ]]>         miriac® MPX-LX2160A https://microsys.de/products/miriac-mpx-lx2160a/ Sat, 22 Feb 2025 11:44:42 +0000 http://zm7h237e.web141.alfahosting-server.de/?post_type=products&p=1642 MicroSys is adding to its successful range of Layerscape® modules with the high-end miriac® MPX-LX2160A.

     

    • NXP® Layerscape® LX2160A with 16 Arm® Cortex®-A72 64-bit cores up to 2.2 GHz
    • 24 SerDes lanes (PCIe Gen3 x8, 100 GbE/40 GbE/25 GbE/10 GbE, SATA)
    • 2x DDR4 controllers (up to 3200 MT/s with ECC) support up to 128 GB DDR4 RAM, ECC
    • Boot select: XSPI, eMMC or external SD card
    • Single 5-12 V DC input supply voltage range

    The post miriac® MPX-LX2160A appeared first on MicroSys.

    ]]>
    Block diagram for MicroSys' System-on-Module miriac® MPX-LX2160A
    CPU
    Architecture Arm® Cortex®-A72
    Processor NXP® Layerscape® LX2160A with 16 Arm® Cortex®-A72 64-bit cores up to 2.2 GHz
    DRAM Up to 128 GB DDR4 RAM & optional ECC, up to 3200MT/sec
    Up to 4 ranks using a combined design: discrete & SODIMM
    Memory
    Flash Up to 2 Gb Octal SPI Flash at up to 200MHz, double operation / golden image
    Flash Card Interface for external SD card
    Boot Flash Boot select: XSPI, eMMC or external SD card
    eMMC Up to 256 GB, HS400, JEDEC 5.1 standard support
    Ethernet
    100GbE Yes
    40GbE Yes
    25GbE Yes
    10 GbE Yes
    100BASE-T1 Yes
    High Speed IO
    SerDes lanes 24 SerDes lanes (PCIe Gen3 x8, 100GbE/40GbE/25GbE/10GbE, SATA)
    USB 3.0 2x
    USB 2.0 Yes
    PCIe PCIe Gen3 x8
    SATA Yes
    IO
    FlexSPI 1x
    UART 2x
    CAN FD 2x
    I2C 2x
    GPIOs Yes
    JTAG Debug Interface Yes
    Security / Safety
    Security Secure boot, trust zone
    Operating Condition
    Power Supply Voltage Single 5 to 12 V DC input supply voltage range
    Typical Power Consumption 25W
    Power Management Yes
    RTC PCF85263
    Temperature 0 °C to 70 °C
    Optional Extended Temperature -40 °C to +85 °C
    Mechanical
    Dimensions 155 x 110 mm
    Connector Type 2x high-speed/high-density open-pin-field connectors á 400 pins
    Software / Additional
    Software Support
  • Linux
  • VxWorks (on request)
  • Others (on request)
    •
    Additional
  • Temperature sensors, cooling controller, RTC, Management Engine
  • All I/O pins available on SEARAY™ Connectors
  • Development Kit available for immediate start; includes power supply, cables; Linux on SD card
    •
    Our standard product versions offer what we consider to be the optimum configuration in terms of performance, price, usage and TDP. The product features lists specify the maximum range of functions per interface. However, not all interfaces or functions are always available in parallel. Flexible SERDES multiplexing is one of the reasons for this. In addition, we provide multiple memory expansion options and are also happy to accommodate specific customer wishes. So do not hesitate to contact us directly to discuss your desired configuration.
    Name Code Description Status
    miriac® MPX-LX2160A 858405 miriac® MPX-LX2160A (3.5.3) 16 Arm Cortex® A72, 2.0 GHz, 32 GB DDR4 w ECC, 16 MB NOR Flash, 512 MB NAND Flash, 32 GB eMMC, -40 °C to 85 °C, w SEC active
    Development Kit basic for miriac® MPX-LX2160A 8597
  • miriac® MPX-LX2160A
  • CRX08
  • incl. BSP and accessories
    •      		active
    Block Diagram
    BSP: SCARTHGAP-6.8.3
    Manual

    Q: In our environment, we need solutions that are available over a very long period of time (up to 15 years). How long are your modules available?

    A: Using NXP CPUs on our SoMs we are able to provide an availability of 15 years from the time of the launch of the CPU. With LTB and long-time stocking we are even able to extend this period.

    The post miriac® MPX-LX2160A appeared first on MicroSys.

    ]]>         miriac® MPX-LS1046A https://microsys.de/products/miriac-mpx-ls1046a/ Fri, 21 Feb 2025 18:50:06 +0000 https://zm7h237e.web141.alfahosting-server.de/?post_type=products&p=5243 Low energy class server module with quad Arm® Cortex®-A72 cores and up to two 10 GbE

     

    • 4 Arm® Cortex®-A72 64-bit cores at up to 1.6 GHz core frequency
    • Up to 8 GB 64-bit DDR4 ECC RAM at 2100 MTps
    • On-board QSPI NOR flash for a reliable boot process
    • Temperature sensor
    • All on board supply voltages are monitored by a separate µ-controller
    • Control of on board voltages and the reset logic offer a wide spectrum of custom functionality, even low level safety functions

    The post miriac® MPX-LS1046A appeared first on MicroSys.

    ]]>
    MPX-LS1046A-R1-Blockdiagram_Folie2
    NXP_LS1046A-BD
    CPU
    Architecture Arm® Cortex®-A72
    Processor NXP® QorIQ® LS1046A CPU: 4 ARM® Cortex®-A72 64-bit cores at up to 1.6 GHz core frequency
    DRAM Up to 8 GB 64-bit DDR4 ECC RAM at 2100 MT/s
    Memory
    Flash up to 2 GB SLC NAND Flash & up to 64 MB QuadSPI Flash
    Flash Card SDHC
    Boot Flash QSPI, SD/MMC, NAND Flash
    eMMC 8-bit
    EEPROM Yes
    Ethernet
    10GbE 2x XFI
    RGMII 2x
    SGMII 5x 1 Gbps, 3x 2.5 Gbps
    QSGMII 1x 5 Gbs
    TSN / IEEE 1588 Yes
    High Speed IO
    SerDes lanes 8x SerDes lanes at 10 Gbps
    USB 3.0 3x (Host / Client / OTG)
    PCIe 3x PCIe Gen3 (x4lane support)
    SATA 1x GEN3
    IO
    FlexSPI 1x
    UART 2x DUART
    I2C 2x
    GPIOs Yes
    JTAG Debug Interface Yes
    Security / Safety
    Security Security Engine (SEC) SFP, CSU
    Operating Condition
    Power Supply Voltage Single 5 to 12 V DC input supply voltage range
    Typical Power Consumption 7W
    Power Management Yes
    RTC Epson RX-8803LC
    Temperature 0 °C to 70 °C
    Optional Extended Temperature -40 °C to +85 °C
    Mechanical
    Dimensions 62 mm x 82 mm
    Connector Type MPX-2 for MXM3.0 socket
    Software / Additional
    Software Support
  • Linux
  • VxWorks (on request)
  • Others (on request)
    •
    Additional
  • Compatible variants available with QorIQ LS1023A, LS1043A, LS1048A, LS1088A
  • Temperature sensor
  • Dev Kit available for immediate start, includes power supply, cables. Linux on SD card
    •
    Our standard product versions offer what we consider to be the optimum configuration in terms of performance, price, usage and TDP. The product features lists specify the maximum range of functions per interface. However, not all interfaces or functions are always available in parallel. Flexible SERDES multiplexing is one of the reasons for this. In addition, we provide multiple memory expansion options and are also happy to accommodate specific customer wishes. So do not hesitate to contact us directly to discuss your desired configuration.
    Name Code Description Status
    miriac® MPX-LS1046A 855615 4 Arm® Cortex®-A72, 1.6 GHz, 4 GB DDR4 w ECC, 16 MB NOR Flash, 512 MB NAND Flash, 0 °C to 70 °C, w/o SEC, MCU 10 Gbit/s active
    Development Kit basic for miriac® MPX-LS1046A 8559
  • miriac® MPX-LS1046A
  • CRX05
  • incl. BSP and accessories
    •      		active
    Development Kit basic for miriac® MPX-LS1043A2 8564
  • miriac® MPX-LS1043A2
  • CRX05
  • incl. BSP and accessories
    •      		active
    Block Diagrams
    BSP: SCARTHGAP-6.8.3
    Manual

    Q: We do not get Secure Boot working

    A: Please verify which version of the processor you have since U-Boot outputs the System Version Register (SVR) which identifies the processor (including revision level).  The SVR is contained in the line after the U-Boot version and starts with “SoC:” See attached screenshot. There are Versions of the SoMs which are assembled with LS1043A processors which do not have a Security Engine (SEC) and the SEC is needed for Secure Boot.

    Q: Inside LS10xx there is an engine that offloads the main CPU regarding the packet forwarding-routing between the MAC interfaces. Where can I get the microcode for this engine?

    A: What you are referring to is the FMan microcode firmware. There are various versions of this depending on end-application. See FMan_uCode_README. Customer can download firmware from https://github.com/NXP/qoriq-fm-ucode

    Q: Is there software available which will exercise the various CPU interfaces? Something like benchmarking or burn-in test software. The purpose is we want to measure the SOM power consumption while the CPU is being exercised.

    A: There is a 10mOhm shunt on the base-board CRX-05 for this purpose. We use the StressAppTest software. Sources can be found here: Github Stressapptest

    Q: I have a question about security fuse programming. It looks like the SOM ST2 header will be used for this purpose. My understanding is that 1.8V needs to be supplied to the PROG-SFP pin during programming. Is the 1.8V supply from ST2 pin 1 sufficient to provide this programming power? In other words can we simply use a mating cable which loops ST2 pin 1 to pin2 for programming?

    A: Yes, you can simply loop ST2 pin1 to pin2 for programming. However, note that you must first boot the board normally and then apply the 1.8V to program the fuses. Meaning that you cannot put a jumper over those 2 pins and then power the board on.

    Q: How can we adapt the Reset Configuration Word (RCW) to our base board?

    A: Check out the sources https://source.codeaurora.org/external/qoriq/qoriq-components/rcw with the following commit number:
    bd6675518e6cb22f731c53407cc0631aa240f49f -> LSDK-20.12
    After that, apply the MicroSys patches. The patches can be found under our Yocto meta layer directory “meta-microsys-layerscape/recipes-bsp/rcw/rcw“. After that you can adopt the RCW : e.g. rcw/mpxls1043/nand/MPX-LS1043A2_C1600_D1600_P400_3358_NAND.rcw In the rcw/mpxls1043/ls1043a.rcwi file you will find all the reset configuration pins that can be set.

    Q: I have a question regarding the 1.8V GPIOs. We currently use the following GPIOs GPIO4, GPIO5, GPIO6, GPIO7, GPIO8. What mechanism can I use to access them in Linux?

    A: On the Command line you can… Read more ≫

    Q: We are trying to bring up the SPI interface. Enabling SPI in the device tree results in the following error messages:
    [ 3.155114] fsl-dspi 2100000.dspi: can‘t get bus-num
    [ 3.160085] fsl-dspi: probe of 2100000.dspi failed with error -22
    We have verified that RCW[SPI_EXT]=000 and RCW[SPI_BASE]=00. What are we missing?

    A: Basically you need an entry in your Device Tree… Read more ≫

    Q: We are using MicroSys LS1046 CPU board, and we built our own baseboard, now we have a problem with ethernet.We are using only one Marvell 88E1512 PHY which has RGMII interface, the PHY address was set to 5’h0, but your CRX05 Baseboard has 4 88E1512 PHYs, 1 PHY in RGMII, and it is PHY address is 5’h03, so our Ethernet doesn’t work.

    My question:

    1) How can we set the our 88E1512 PHY address to 5’h03 to match your software, ( as I downloaded the latest 88E1512 Datasheet, Marvell says this PHY address can only be 5’h0 or 5’h1, how did you set your RGMII PHY address to 5‘h3)

    2) Or What SW code needs to be changed to tell the SW(Unoot/Linux) to use RGMII PHY at address 5’h3 to make it work, we tried to change your hardcoded PHY address mapping to 5’h0 (in uboot\git\include\configs \mpxls1046.h), but it still doesn’t work

    A: First, a general comment. Whenever you design… Read more ≫

    Q: I am in the process of bringing up my SOM carrier board and I have a question. My design has two Ethernet PHYs (88E1512) connected to each of the SOM’s RGMII interfaces (block diagram attached), but neither RGMII interface is able to establish a link. U-boot is reporting that the LS1046A MAC #9 and #6 have been assigned to these ports (shown below). But your documentation shows that only MAC #3 and #4 supports RGMII. How do I change my MAC assignment to #3 and #4?

    A: The network setup for U-Boot on MPXLS1046 is done in eth.c in boards/microsys/mpxls1046 located in the U-Boot source tree. In this file there is a function called board_eth_init(). This function does the network setup for U-Boot. There you have to tell U-Boot which network interfaces are enabled or disabled and how the PHYs are connected to the interfaces. Please review this function and adjust everything according to your carrier.

    Q: We have the need to change the thermal shutdown limit to 95° C. May I ask for instructions on how to do that?

    A: Linux command “sensors” can be used to show temp. temp1 is the TMP451 Sensor chip and temp2 measures the temperature at the substrate of the LS1046A.
    root@mpxls1046:/sys/class/i2c-adapter/i2c-0/0-004c/hwmon/hwmon0# sensors lm90-i2c-0-4c
    Adapter: 2180000.i2c
    temp1: +60.0 C (low = +0.0 C, high = +85.0 C) (crit = +85.0 C, hyst = +75.0 C)
    temp2: +63.5 C (low = +0.0 C, high = +85.0 C) (crit = +108.0 C, hyst = +98.0 C)

    Q: I want to read or write internal phy registers under Linux with phytool utility but it’s not running. It returns to me the following message
    # phytool read eth0/0/5

    error: phy_read (-22)

    These regiters are accessible under uboot. What’s happening ? How you read or write these registers under Linux ?

    A: Don’t include phytool in the standard rootfs but you can download it to the target, build it and run it.
    # unzip phytool-master.zip
    # cd phytool-master
    # make all
    # ./phytool read fm1-mac3/3/2

    Q: Just reaching out to you to see if you could offer up some help to our software guys. We are working on our encryption throughput and having troubles determining whether we are making use of all 4 cores in this processor or just one. Would you have any assistance you could offer on this topic? Is there a way for us to see which cores we are making use of?

    A: For CPU utilisation you can use the linux command mpstat.
    For example:
    # mpstat -P ALL 1
    NXP documentation “QORIQ-SDK-2.0-IC-REV0.pdf”, chapter 9.7 describes how to set up the encryption engine: https://www.nxp.com/docs/en/supporting-information/QORIQ-SDK-2.0-IC-REV0.pdf

    Q: I have a question for the RGMII bus on the LS1046. The only requirement I’ve found for the PCB layout is https://community.nxp.com/thread/447516
    but is the part that is routed on the SOM already matched in length or should the trace length on our main board be compensated for this ?

    A: You will find all required timings in the NXP documentation QorIQ LS1046A, LS1026A Data Sheet, Rev. 0, 02/2017 or later revisions. Chapter 3.10.6.2 RGMII AC timing specifications says “Data to clock input skew at transceiver” shall be 1.0<x<2.6ns and notes that at least 1.5ns shall be applied. We have no such delay implemented on the SOM but this needs to be done on the base board. (Receiver)

    In order to avoid ~30cm of trace length (with the possibility for adjustments) most PHY’s have implemented a pad delay register for adjustment.

    e.g. Marvell 88E1512 provides:

    „Four RGMII timing modes including integrated delays – This eliminates the need for adding trace delays on the PCB“.

    Please check if the PHY you use provides for such compensation

    Q: In our environment, we need solutions that are available over a very long period of time (up to 15 years). How long are your modules available?

    A: Using NXP CPUs on our SoMs we are able to provide an availability of 15 years from the time of the launch of the CPU. With LTB and long-time stocking we are even able to extend this period.

    The post miriac® MPX-LS1046A appeared first on MicroSys.

    ]]>         miriac® MPX-LS1043A https://microsys.de/products/miriac-mpx-ls1043a/ Fri, 21 Feb 2025 13:30:46 +0000 https://zm7h237e.web141.alfahosting-server.de/?post_type=products&p=4356 A performance boost over dual-core Arm® 32-bit processors and continuing the QorIQ® legacy of I/O flexibility.

     

    • 4 Arm® Cortex®-A53 64-bit cores at up to 1.6 GHz core frequency
    • Up to 4 GB 32-bit DDR4 ECC RAM at 1600 MTps
    • Temperature sensor
    • All on board supply voltages are monitored by a separate µ-controller
    • Control of on board voltages and the reset logic offer a wide spectrum of custom functionality, even low level safety functions.

    The post miriac® MPX-LS1043A appeared first on MicroSys.

    ]]>
    MPX-LS1043A-R1-Blockdiagram
    NXP_LS1043A
    CPU
    Architecture Arm® Cortex®-A53
    Processor NXP® QorIQ® LS1043A CPU: 4 Arm® Cortex®-A53 64-bit cores at up to 1.6 GHz core frequency
    DRAM Up to 4 GB 32-bit DDR4 ECC RAM
    Memory
    Flash Up to 2 GB SLC NAND Flash & up to 16 MB SPI Flash
    Flash Card SDHC
    Boot Flash QSPI, SD/MMC, NAND Flash
    eMMC 8-bit
    EEPROM Yes
    Ethernet
    10GbE 1x XFI
    RGMII 2x
    SGMII 4x 1 Gbps, 2x 2.5 Gbps
    QSGMII 2x 5 Gbps
    TSN / IEEE 1588 Yes
    High Speed IO
    SerDes lanes 4x SerDes lanes at 10 Gbps
    USB 3.0 3x
    PCIe 3x PCIe Gen2
    SATA 1x GEN3
    IO
    FlexSPI 1x
    UART 2x DUART
    I2C 2x
    GPIOs Yes
    JTAG Debug Interface Yes
    Security / Safety
    Security Security Engine (SEC) SFP, CSU
    Operating Condition
    Power Supply Voltage Single 5 to 12 V DC input supply voltage range
    Typical Power Consumption 5 W
    Power Management Yes
    RTC Epson RX-8803LC
    Temperature 0 °C to 70 °C
    Optional Extended Temperature -40 °C to +85 °C
    Mechanical
    Dimensions 62 mm x 82 mm
    Connector Type MPX-2 for MXM3.0 socket
    Software / Additional
    Software Support
  • Linux
  • VxWorks (on request)
  • Others (on request)
    •
    Additional
  • Compatible variants available with QorIQ LS1023A, LS1046A, LS1048A, LS1088A
  • Temperature sensor
  • Dev Kit available for immediate start, includes power supply, cables. Linux on SD card
    •

    Our standard product versions offer what we consider to be the optimum configuration in terms of performance, price, usage and TDP. The product features lists specify the maximum range of functions per interface. However, not all interfaces or functions are always available in parallel. Flexible SERDES multiplexing is one of the reasons for this. In addition, we provide multiple memory expansion options and are also happy to accommodate specific customer wishes. So do not hesitate to contact us directly to discuss your desired configuration.

    Name Code Description Status
    miriac® MPX-LS1043A2 855608 4 Arm Cortex® A53, 1.6 GHz, 2 GB DDR4 w ECC, 16 MB NOR Flash, 2 GB NAND Flash, -40 °C to 85 °C, w SEC active
    Development Kit pro for miriac® MPX-LS1043A2 8564xx 4 Arm Cortex® A53, 1.6 GHz, 2 GB DDR4 w ECC, 16 MB NOR Flash, 2 GB NAND Flash, -40 °C to 85 °C, w SEC active
    Development Kit basic for miriac® MPX-LS1043A2 8564xx
  • miriac® MPX-LS1043A2
  • CRX05
  • incl. BSP and accessories
    •      		active
    Block Diagrams
    BSP: SCARTHGAP-6.8.3
    Manual

    Q: We do not get Secure Boot working

    A: Please verify which version of the processor you have since U-Boot outputs the System Version Register (SVR) which identifies the processor (including revision level).  The SVR is contained in the line after the U-Boot version and starts with “SoC:” See attached screenshot. There are Versions of the SoMs which are assembled with LS1043A processors which do not have a Security Engine (SEC) and the SEC is needed for Secure Boot.

    Q: Inside LS10xx there is an engine that offloads the main CPU regarding the packet forwarding-routing between the MAC interfaces. Where can I get the microcode for this engine?

    A: What you are referring to is the FMan microcode firmware. There are various versions of this depending on end-application. See FMan_uCode_README. Customer can download firmware from https://github.com/NXP/qoriq-fm-ucode

    Q: Is there software available which will exercise the various CPU interfaces? Something like benchmarking or burn-in test software. The purpose is we want to measure the SOM power consumption while the CPU is being exercised.

    A: There is a 10mOhm shunt on the base-board CRX-05 for this purpose. We use the StressAppTest software. Sources can be found here: Github Stressapptest

    Q: I have a question about security fuse programming. It looks like the SOM ST2 header will be used for this purpose. My understanding is that 1.8V needs to be supplied to the PROG-SFP pin during programming. Is the 1.8V supply from ST2 pin 1 sufficient to provide this programming power? In other words can we simply use a mating cable which loops ST2 pin 1 to pin2 for programming?

    A: Yes, you can simply loop ST2 pin1 to pin2 for programming. However, note that you must first boot the board normally and then apply the 1.8V to program the fuses. Meaning that you cannot put a jumper over those 2 pins and then power the board on.

    Q: How can we adapt the Reset Configuration Word (RCW) to our base board?

    A: Check out the sources https://source.codeaurora.org/external/qoriq/qoriq-components/rcw with the following commit number:
    bd6675518e6cb22f731c53407cc0631aa240f49f -> LSDK-20.12
    After that, apply the MicroSys patches. The patches can be found under our Yocto meta layer directory “meta-microsys-layerscape/recipes-bsp/rcw/rcw“. After that you can adopt the RCW : e.g. rcw/mpxls1043/nand/MPX-LS1043A2_C1600_D1600_P400_3358_NAND.rcw In the rcw/mpxls1043/ls1043a.rcwi file you will find all the reset configuration pins that can be set.

    Q: I have a question regarding the 1.8V GPIOs. We currently use the following GPIOs GPIO4, GPIO5, GPIO6, GPIO7, GPIO8. What mechanism can I use to access them in Linux?

    A: On the Command line you can… Read more ≫

    Q: We are trying to bring up the SPI interface. Enabling SPI in the device tree results in the following error messages:
    [ 3.155114] fsl-dspi 2100000.dspi: can‘t get bus-num
    [ 3.160085] fsl-dspi: probe of 2100000.dspi failed with error -22
    We have verified that RCW[SPI_EXT]=000 and RCW[SPI_BASE]=00. What are we missing?

    A: Basically you need an entry in your Device Tree… Read more ≫

    Q: We are using MicroSys LS1046 CPU board, and we built our own baseboard, now we have a problem with ethernet.We are using only one Marvell 88E1512 PHY which has RGMII interface, the PHY address was set to 5’h0, but your CRX05 Baseboard has 4 88E1512 PHYs, 1 PHY in RGMII, and it is PHY address is 5’h03, so our Ethernet doesn’t work.

    My question:

    1) How can we set the our 88E1512 PHY address to 5’h03 to match your software, ( as I downloaded the latest 88E1512 Datasheet, Marvell says this PHY address can only be 5’h0 or 5’h1, how did you set your RGMII PHY address to 5‘h3)

    2) Or What SW code needs to be changed to tell the SW(Unoot/Linux) to use RGMII PHY at address 5’h3 to make it work, we tried to change your hardcoded PHY address mapping to 5’h0 (in uboot\git\include\configs \mpxls1046.h), but it still doesn’t work

    A: First, a general comment. Whenever you design… Read more ≫

    Q: I am in the process of bringing up my SOM carrier board and I have a question. My design has two Ethernet PHYs (88E1512) connected to each of the SOM’s RGMII interfaces (block diagram attached), but neither RGMII interface is able to establish a link. U-boot is reporting that the LS1046A MAC #9 and #6 have been assigned to these ports (shown below). But your documentation shows that only MAC #3 and #4 supports RGMII. How do I change my MAC assignment to #3 and #4?

    A: The network setup for U-Boot on MPXLS1046 is done in eth.c in boards/microsys/mpxls1046 located in the U-Boot source tree. In this file there is a function called board_eth_init(). This function does the network setup for U-Boot. There you have to tell U-Boot which network interfaces are enabled or disabled and how the PHYs are connected to the interfaces. Please review this function and adjust everything according to your carrier.

    Q: We have the need to change the thermal shutdown limit to 95° C. May I ask for instructions on how to do that?

    A: Linux command “sensors” can be used to show temp. temp1 is the TMP451 Sensor chip and temp2 measures the temperature at the substrate of the LS1046A.
    root@mpxls1046:/sys/class/i2c-adapter/i2c-0/0-004c/hwmon/hwmon0# sensors lm90-i2c-0-4c
    Adapter: 2180000.i2c
    temp1: +60.0 C (low = +0.0 C, high = +85.0 C) (crit = +85.0 C, hyst = +75.0 C)
    temp2: +63.5 C (low = +0.0 C, high = +85.0 C) (crit = +108.0 C, hyst = +98.0 C)

    Q: I want to read or write internal phy registers under Linux with phytool utility but it’s not running. It returns to me the following message
    # phytool read eth0/0/5

    error: phy_read (-22)

    These regiters are accessible under uboot. What’s happening ? How you read or write these registers under Linux ?

    A: Don’t include phytool in the standard rootfs but you can download it to the target, build it and run it.
    # unzip phytool-master.zip
    # cd phytool-master
    # make all
    # ./phytool read fm1-mac3/3/2

    Q: Just reaching out to you to see if you could offer up some help to our software guys. We are working on our encryption throughput and having troubles determining whether we are making use of all 4 cores in this processor or just one. Would you have any assistance you could offer on this topic? Is there a way for us to see which cores we are making use of?

    A: For CPU utilisation you can use the linux command mpstat.
    For example:
    # mpstat -P ALL 1
    NXP documentation “QORIQ-SDK-2.0-IC-REV0.pdf”, chapter 9.7 describes how to set up the encryption engine: https://www.nxp.com/docs/en/supporting-information/QORIQ-SDK-2.0-IC-REV0.pdf

    Q: I have a question for the RGMII bus on the LS1046. The only requirement I’ve found for the PCB layout is https://community.nxp.com/thread/447516
    but is the part that is routed on the SOM already matched in length or should the trace length on our main board be compensated for this ?

    A: You will find all required timings in the NXP documentation QorIQ LS1046A, LS1026A Data Sheet, Rev. 0, 02/2017 or later revisions. Chapter 3.10.6.2 RGMII AC timing specifications says “Data to clock input skew at transceiver” shall be 1.0<x<2.6ns and notes that at least 1.5ns shall be applied. We have no such delay implemented on the SOM but this needs to be done on the base board. (Receiver)

    In order to avoid ~30cm of trace length (with the possibility for adjustments) most PHY’s have implemented a pad delay register for adjustment.

    e.g. Marvell 88E1512 provides:

    „Four RGMII timing modes including integrated delays – This eliminates the need for adding trace delays on the PCB“.

    Please check if the PHY you use provides for such compensation

    Q: In our environment, we need solutions that are available over a very long period of time (up to 15 years). How long are your modules available?

    A: Using NXP CPUs on our SoMs we are able to provide an availability of 15 years from the time of the launch of the CPU. With LTB and long-time stocking we are even able to extend this period.

    The post miriac® MPX-LS1043A appeared first on MicroSys.

    ]]>         miriac® MPX-LS1088A https://microsys.de/products/miriac-mpx-ls1088a/ Tue, 18 Feb 2025 18:49:17 +0000 https://zm7h237e.web141.alfahosting-server.de/?post_type=products&p=4293 Module with advanced, high-performance data path and network peripheral interfaces

     

    • 8 Arm® Cortex®-A53 64-bit cores at up to 1.6 GHz core frequency
    • Up to 8 GB 64-bit DDR4 ECC RAM at 2100 MTps
    • Temperature sensor
    • All on board supply voltages are monitored by a separate µ-controller
    • Control of on-board voltages and the reset logic offer a wide spectrum of custom functionality, even low-level safety functions

    The post miriac® MPX-LS1088A appeared first on MicroSys.

    ]]>
    MPX-LS1088A-R1-Blockdiagram
    NXP_LS1088A-BLOCK-DIAGRAM
    CPU
    Architecture Arm® Cortex®-A53
    Processor NXP® QorIQ® LS1088A CPU: 8-Arm® Cortex®-A53 64-bit cores at up to 1.6 GHz core frequency
    DRAM Up to 8 GB 32-bit DDR4 ECC RAM at 2100 MT/s
    Memory
    Flash Up to 2 GB SLC NAND Flash & up to 64 MB QuadSPI Flash
    Flash Card SDHC
    Boot Flash QSPI, SD/MMC, NAND Flash
    eMMC 8-bit
    EEPROM Yes
    Ethernet
    10GbE 2x XFI
    RGMII 2x
    SGMII 8x 1 Gbps, 2x 2.5 Gbps
    QSGMII 2x 5Gbs
    TSN / IEEE 1588 Yes
    High Speed IO
    SerDes lanes 8x SerDes lanes at 10 Gbps
    USB 3.0 3x (Host / Client / OTG)
    PCIe 3x PCIe Gen3 (x4lane support)
    SATA 1x GEN3
    IO
    FlexSPI 1x
    UART 2x DUART
    I2C 2x
    GPIOs Yes
    JTAG Debug Interface Yes
    Security / Safety
    Security Security Engine (SEC) SFP, CSU
    Operating Condition
    Power Supply Voltage Single 5 to 12 V DC input supply voltage range
    Typical Power Consumption 8.5 W
    Power Management Yes
    RTC Epson RX-8803LC
    Temperature 0 °C to 70 °C
    Optional Extended Temperature -40 °C to +85 °C
    Mechanical
    Dimensions 62 mm x 82 mm
    Connector Type MPX-2 for MXM3.0 socket
    Software / Additional
    Software Support
  • Linux
  • VxWorks (on request)
  • Others (on request)
    •
    Additional
  • Compatible variants available with QorIQ® LS1023A, LS1043A, LS1046A, LS1048A
  • Temperature sensor
  • Dev Kit available for immediate start, includes power supply, cables. Linux on SD card
    •

    Our standard product versions offer what we consider to be the optimum configuration in terms of performance, price, usage and TDP. The product features lists specify the maximum range of functions per interface. However, not all interfaces or functions are always available in parallel. Flexible SERDES multiplexing is one of the reasons for this. In addition, we provide multiple memory expansion options and are also happy to accommodate specific customer wishes. So do not hesitate to contact us directly to discuss your desired configuration.

    Name Code Description Status
    miriac® MPX-LS1088A 855606 8 Arm® Cortex®-A53, 1.6 GHz, 4 GB DDR4 w ECC, 16 MB NOR Flash, 512 MB Flash, 0 °C to 70 °C, w SEC active
    Development Kit basic for miriac® MPX-LS1088A 8559xx
  • miriac® MPX-LS1088A
  • CRX05
  • incl. BSP and accessories
    •      		active
    Development Kit basic for miriac® MPX-LS1088A 8559xx
  • miriac® MPX-LS1088A
  • CRX06-TSN
  • incl. BSP and accessories
    •      		active
    Block Diagrams
    BSP: SCARTHGAP-6.8.3
    Manual

    Q: We do not get Secure Boot working

    A: Please verify which version of the processor you have since U-Boot outputs the System Version Register (SVR) which identifies the processor (including revision level). The SVR is contained in the line after the U-Boot version and starts with “SoC:” See attached screenshot. There are Versions of the SoMs which are assembled with LS1043A processors which do not have a Security Engine (SEC) and the SEC is needed for Secure Boot.

    Q: Inside LS10xx there is an engine that offloads the main CPU regarding the packet forwarding-routing between the MAC interfaces. Where can I get the microcode for this engine?

    A: What you are referring to is the FMan microcode firmware. There are various versions of this depending on end-application. See FMan_uCode_README. Customer can download firmware from https://github.com/NXP/qoriq-fm-ucode

    Q: Is there software available which will exercise the various CPU interfaces? Something like benchmarking or burn-in test software. The purpose is we want to measure the SOM power consumption while the CPU is being exercised.

    A: There is a 10mOhm shunt on the base-board CRX-05 for this purpose. We use the StressAppTest software. Sources can be found here: Github Stressapptest

    Q: I have a question about security fuse programming. It looks like the SOM ST2 header will be used for this purpose. My understanding is that 1.8V needs to be supplied to the PROG-SFP pin during programming. Is the 1.8V supply from ST2 pin 1 sufficient to provide this programming power? In other words can we simply use a mating cable which loops ST2 pin 1 to pin2 for programming?

    A: Yes, you can simply loop ST2 pin1 to pin2 for programming. However, note that you must first boot the board normally and then apply the 1.8V to program the fuses. Meaning that you cannot put a jumper over those 2 pins and then power the board on.

    Q: How can we adapt the Reset Configuration Word (RCW) to our base board?

    A: Check out the sources https://source.codeaurora.org/external/qoriq/qoriq-components/rcw with the following commit number:
    bd6675518e6cb22f731c53407cc0631aa240f49f -> LSDK-20.12
    After that, apply the MicroSys patches. The patches can be found under our Yocto meta layer directory “meta-microsys-layerscape/recipes-bsp/rcw/rcw“. After that you can adopt the RCW : e.g. rcw/mpxls1043/nand/MPX-LS1043A2_C1600_D1600_P400_3358_NAND.rcw In the rcw/mpxls1043/ls1043a.rcwi file you will find all the reset configuration pins that can be set.

    Q: I have a question regarding the 1.8V GPIOs. We currently use the following GPIOs GPIO4, GPIO5, GPIO6, GPIO7, GPIO8. What mechanism can I use to access them in Linux?

    A: On the Command line you can… Read more ≫

    Q: We are trying to bring up the SPI interface. Enabling SPI in the device tree results in the following error messages:
    [ 3.155114] fsl-dspi 2100000.dspi: can‘t get bus-num
    [ 3.160085] fsl-dspi: probe of 2100000.dspi failed with error -22
    We have verified that RCW[SPI_EXT]=000 and RCW[SPI_BASE]=00. What are we missing?

    A: Basically you need an entry in your Device Tree… Read more ≫

    Q: We are using MicroSys LS1046 CPU board, and we built our own baseboard, now we have a problem with ethernet.We are using only one Marvell 88E1512 PHY which has RGMII interface, the PHY address was set to 5’h0, but your CRX05 Baseboard has 4 88E1512 PHYs, 1 PHY in RGMII, and it is PHY address is 5’h03, so our Ethernet doesn’t work.

    My question:

    1) How can we set the our 88E1512 PHY address to 5’h03 to match your software, ( as I downloaded the latest 88E1512 Datasheet, Marvell says this PHY address can only be 5’h0 or 5’h1, how did you set your RGMII PHY address to 5‘h3)

    2) Or What SW code needs to be changed to tell the SW(Unoot/Linux) to use RGMII PHY at address 5’h3 to make it work, we tried to change your hardcoded PHY address mapping to 5’h0 (in uboot\git\include\configs \mpxls1046.h), but it still doesn’t work

    A: First, a general comment. Whenever you design… Read more ≫

    Q: I am in the process of bringing up my SOM carrier board and I have a question. My design has two Ethernet PHYs (88E1512) connected to each of the SOM’s RGMII interfaces (block diagram attached), but neither RGMII interface is able to establish a link. U-boot is reporting that the LS1046A MAC #9 and #6 have been assigned to these ports (shown below). But your documentation shows that only MAC #3 and #4 supports RGMII. How do I change my MAC assignment to #3 and #4?

    A: The network setup for U-Boot on MPXLS1046 is done in eth.c in boards/microsys/mpxls1046 located in the U-Boot source tree. In this file there is a function called board_eth_init(). This function does the network setup for U-Boot. There you have to tell U-Boot which network interfaces are enabled or disabled and how the PHYs are connected to the interfaces. Please review this function and adjust everything according to your carrier.

    Q: We have the need to change the thermal shutdown limit to 95° C. May I ask for instructions on how to do that?

    A: Linux command “sensors” can be used to show temp. temp1 is the TMP451 Sensor chip and temp2 measures the temperature at the substrate of the LS1046A.
    root@mpxls1046:/sys/class/i2c-adapter/i2c-0/0-004c/hwmon/hwmon0# sensors lm90-i2c-0-4c
    Adapter: 2180000.i2c
    temp1: +60.0 C (low = +0.0 C, high = +85.0 C) (crit = +85.0 C, hyst = +75.0 C)
    temp2: +63.5 C (low = +0.0 C, high = +85.0 C) (crit = +108.0 C, hyst = +98.0 C)

    Q: I want to read or write internal phy registers under Linux with phytool utility but it’s not running. It returns to me the following message
    # phytool read eth0/0/5

    error: phy_read (-22)

    These regiters are accessible under uboot. What’s happening ? How you read or write these registers under Linux ?

    A: Don’t include phytool in the standard rootfs but you can download it to the target, build it and run it.
    # unzip phytool-master.zip
    # cd phytool-master
    # make all
    # ./phytool read fm1-mac3/3/2

    Q: Just reaching out to you to see if you could offer up some help to our software guys. We are working on our encryption throughput and having troubles determining whether we are making use of all 4 cores in this processor or just one. Would you have any assistance you could offer on this topic? Is there a way for us to see which cores we are making use of?

    A: For CPU utilisation you can use the linux command mpstat.
    For example:
    # mpstat -P ALL 1
    NXP documentation “QORIQ-SDK-2.0-IC-REV0.pdf”, chapter 9.7 describes how to set up the encryption engine: https://www.nxp.com/docs/en/supporting-information/QORIQ-SDK-2.0-IC-REV0.pdf

    Q: I have a question for the RGMII bus on the LS1046. The only requirement I’ve found for the PCB layout is https://community.nxp.com/thread/447516
    but is the part that is routed on the SOM already matched in length or should the trace length on our main board be compensated for this ?

    A: You will find all required timings in the NXP documentation QorIQ LS1046A, LS1026A Data Sheet, Rev. 0, 02/2017 or later revisions. Chapter 3.10.6.2 RGMII AC timing specifications says “Data to clock input skew at transceiver” shall be 1.0<x<2.6ns and notes that at least 1.5ns shall be applied. We have no such delay implemented on the SOM but this needs to be done on the base board. (Receiver)

    In order to avoid ~30cm of trace length (with the possibility for adjustments) most PHY’s have implemented a pad delay register for adjustment.

    e.g. Marvell 88E1512 provides:

    „Four RGMII timing modes including integrated delays – This eliminates the need for adding trace delays on the PCB“.

    Please check if the PHY you use provides for such compensation

    Q: In our environment, we need solutions that are available over a very long period of time (up to 15 years). How long are your modules available?

    A: Using NXP CPUs on our SoMs we are able to provide an availability of 15 years from the time of the launch of the CPU. With LTB and long-time stocking we are even able to extend this period.

    The post miriac® MPX-LS1088A appeared first on MicroSys.

    ]]>         miriac® MPX-LS1028A (EOL) https://microsys.de/products/miriac-mpx-ls1028a/ Tue, 18 Feb 2025 16:00:45 +0000 https://zm7h237e.web141.alfahosting-server.de/?post_type=products&p=4218 It combines high compute power by two powerful 64-bit Arm® Cortex®-A72 cores with TSN based Real Time Ethernet communication.

     

    • Two 64-bit Arm® Cortex®-A72 cores
    • TSN based Real Time Ethernet communication
    • Security engine
    • Integrated graphics unit for HMI functions
    • Small, highly integrated SoM, a perfect fit for IIoT devices and nodes

    The post miriac® MPX-LS1028A (EOL) appeared first on MicroSys.

    ]]>
    MPX-LS1028A-R2-Blockdiagram
    LS1028A-BD
    CPU
    Architecture Arm® Cortex®-A72
    Processor NXP® QorIQ® LS1028A CPU: 2 Arm® Cortex®-A72 64-bit cores at up to 1.5 GHz core frequency
    DRAM Up to 4 GB 32-bit DDR4 ECC RAM 1600 MT/s
    Memory
    Flash Up to 256 MB Serial NOR Flash & up to 512 MB Serial NAND Flash
    Flash Card 2x SDHC
    Boot Flash SDHC, eMMC, XSPI, NAND Flash
    eMMC 8-bit
    EEPROM Yes
    Graphic
    Graphics Controller Yes
    Display Display Port 1.3 and eDP1.4
    Ethernet
    10GbE 1x SXGMII / QXGMII
    RGMII 1x
    SGMII 4x 1.25 Gbps
    QSGMII 1x 5 Gbps
    TSN / IEEE 1588 Yes (4 Port TSN Switch on board) IEEE 802.1
    High Speed IO
    SerDes lanes 4x SerDes lanes at 10 Gbps
    USB 3.0 2x
    PCIe 4x PCIe Gen3
    SATA 1x GEN3
    IO
    FlexSPI 3x
    UART 2x
    CAN FD 2x
    I2C 8x
    Audio Yes (SAI)
    GPIOs Yes
    JTAG Debug Interface Yes
    Security / Safety
    Security Trust Architecture
    Operating Condition
    Power Supply Voltage Single 5 V DC input supply voltage range
    Typical Power Consumption 5W
    Power Management Yes
    RTC PCF85063
    Temperature 0 °C to 70 °C
    Optional Extended Temperature -40 °C to +85 °C
    Mechanical
    Dimensions 45 mm x 62 mm
    Connector Type 230 pin 0.5 mm pitch
    Software / Additional
    Software Support
  • Linux
  • VxWorks (on request)
  • Others (on request)
    •
    Additional Graphics processing unit:
  • Supports Geometry rate 100 Mtri/sec, Pixel rate 650 Mpixel/sec, GFLOPS(32-bit high precision) = 10.4
  • Supports OpenGL ES 3.0, 2.0, 1.1
  • Supports OpenCL 1.1, 1.2

  • Compatible variants available with QorIQ® LS1018A
  • Temperature sensor
  • Dev Kit available for immediate start, includes power supply, cables
  • Linux on SD card
    •
    Our standard product versions offer what we consider to be the optimum configuration in terms of performance, price, usage and TDP. The product features lists specify the maximum range of functions per interface. However, not all interfaces or functions are always available in parallel. Flexible SERDES multiplexing is one of the reasons for this. In addition, we provide multiple memory expansion options and are also happy to accommodate specific customer wishes. So do not hesitate to contact us directly to discuss your desired configuration.
    Name Code Description Status
    miriac® MPX-LS1028A 857001 2 Arm® Cortex®-A72, 1.3 GHz, 4 GB DDR4 w ECC, 16 MB NOR Flash, 512 MB Nand Flash, 0 °C to 70 °C, w SEC EOL
    Development Kit basic for miriac® MPX-LS1028A 8576xx
  • miriac® MPX-LS1028A
  • CRX07-TSN
  • incl. BSP and accessories
    •      		EOL
    Block Diagrams
    BSP: KIRKSTONE-5.9.2
    Manual

    Q: It is unclear whether the SAI blocks are Slave only or do they support Master mode too?

    A: The SAI blocks work in Slave mode only

    Q: We expect to configure the SAI in Synchronous mode and each of the peripheral shown has 5 critical signals (Bit Clk, Fsync, Din Dout & Mclk). The SAI blocks however has 7 signals (TX Bit Clk, RX Bit Clk , TX Fsync, RX Fsync, TX Data, RX Data & Mclk). How does the mapping work in this case?

    A: SAI Block has 6 signals (TX Bit Clk, RX Bit Clk , TX Fsync, RX Fsync, TX Data, RX Data) and TX signals are multiplexed with Rx signals. Hence only one can be used at a time.This requires that 2 SAI modules are used per CODEC.

    Q: For instance TX Data & RX Data are mapped to the same physical pin on the SOC, (SAI4 TX_DATA and RX_DATA mapped to EC1_TXD2) how do I map 2 external signals to a single pin on SOC?

    A: Using RCW

    Q: In our environment, we need solutions that are available over a very long period of time (up to 15 years). How long are your modules available?

    A: Using NXP CPUs on our SoMs we are able to provide an availability of 15 years from the time of the launch of the CPU. With LTB and long-time stocking we are even able to extend this period.

    RCW[EC1_SAI4_5_PMUX] = 0b010 – { SAI5_TX_DATA, SAI4_TX_DATA, SAI5_TX_SYNC, SAI4_TX_SYNC, SAI5_TX_BCLK, SAI4_TX_BCLK}

    RCW[EC1_SAI4_5_PMUX] = 0b011 – {SAI5_RX_DATA, SAI4_RX_DATA, SAI5_RX_SYNC, SAI4_RX_SYNC,SAI5_RX_BCLK, SAI4_RX_BCLK}

    The post miriac® MPX-LS1028A (EOL) appeared first on MicroSys.

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